A known disk array apparatus performs write back cache in order to reduce the waiting time of a host computer that performs read/write access on the disk array apparatus.
The term “write back cache” refers to a processing operation in which an MPU (micro processing unit) in the apparatus temporarily writes, before writing data to a HDD (hard disk drive), the data to a high-speed accessible cache memory and writes back the data from the cache memory to the HDD later during idle time.
Since the cache memory is a volatile memory, the data that remains in the cache memory needs to be saved somewhere without a loss of the data, in the case of a power loss due to a power failure or the like. For the write cache back, it is important to ensure the safety of the cache data that has not been written to the HDD and that remains in the cache memory.
In particular, in a disk array apparatus equipped with a large-capacity cache memory in order to increase the speed of the read/write access from the host computer, a large amount of cache data is written to the cache memory. This makes it even more important to ensure the safety of the cache data.
Japanese Laid-Open Patent Application Publication (Translation of PCT Application) No. 2004-531814 discloses a scheme in which, when a power failure occurs, user data stored in a cache memory is saved into a flash memory which is a nonvolatile memory before the apparatus completely loses power. Thereafter, when power is restored, the cache data is restored from the flash memory into the cache memory.
The backup data saved in the flash memory requires deletion processing after power is restored and the data is restored in the cache memory, in preparation for a next power failure. This is because the flash memory does not permit data writing unless it is initialized.
The problem in this case is that, when a power failure occurs again during the deletion processing and the disk array apparatus is turned off without backup of the deleted data, the data is completely lost and thus cannot be restored into the cache memory.
When the scheme disclosed in Japanese Laid-Open Patent Application Publication No. 2004-531814 is applied to a disk array apparatus, a large-capacity flash memory is required and a large amount of backup data is written to the flash memory during a power failure. In this case, the deletion processing of the flash memory may take several tens of seconds to several minutes, during which the risk of occurrence of a power failure also increases. Thus, it is also important to ensure the safety of data deleted.
One possible approach is that, when power supply from a main power source is lost due to a power failure, the remaining deletion processing is completed using power supplied from a battery so that the flash memory is writable, and the cache data restored in the cache memory is backed up again. This processing operation, however, requires a large amount of power and thus has the problem of increased cost of the battery.
Another possible approach is that backup data is written to one of two flash memories during a power failure and deletion processing is then performed on the flash memory in which the backup data is written, in preparation for a next power failure. With this arrangement, even if a power failure occurs during the deletion processing of the flash memory, the backup data is safely stored since no deletion processing has been performed on the other flash memory used for backing up data this time. The use of the two flash memories, however, has the problem of increased cost.